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| (R) P r o PA107DPt i o n F r o m duct Innova PA107DP PA107DP GENERAL DESCRIPTION Power Operational Amplifiers FEATURES Power Bandwidth 170 VP-P, 2 MHz Output Voltage up to 180 Vp-p High Slew Rate 2500 V/s Minimum with A CL = 20 High Gain Bandwidth Product 180 MHz High Output Current 1.5 A Steady State Within SOA High Peak Output Current 5 A The PA107DP is a state of the art wideband high power operational amplifier designed to drive resistive, capacitive or inductive loads. For optimum linearity the output stage is biased for class A/B operation. Feed forward technology is used to obtain wide bandwidth and excellent DC performance, but constricts use to inverting mode only. External compensation allows the user to obtain both high gain and wide bandwidth. Use of a heatsink is required to realize the SOA. This hybrid integrated circuit uses thick film resistors, ceramic capacitors, and semiconductors to maximize reliability, minimize size, and give top performance. Ultrasonically bonded aluminum wires provide reliable interconnections at all operating temperatures. The 12 pin SIP package occupies only 2 square inches. The use of compressible insulation washers voids the warranty. APPLICATIONS Piezo Drive CRT Beam Intensity Control ATE Applications Line Driver EQUIVALENT SCHEMATIC +VAUX R4 Q10 R18 Q4 Q5 D5 -VAUX Q2 D7 Q8 Q11 Q20 D1 D IN 1 R1 G C2 Q1:1 S D G -VAUX 3 -VAUX R2 D3 Q1:2 S +VAUX + U1 GND 4 C1 R3 VEE D2 C3 D4 Q13 D10 -VS R9 R13 R17 Q22 9 -VS D6 Q6 10 Q7 R19 Q12 Q9 Q15 Q18 -VSP +VAUX Q3 C5 R8 R11 D8 Q21 C4 R7 R10 Q14 Q17 12 +Vsp +VS D9 R6 R12 R16 Q19 8 +VS +VAUX 2 +VAUX R14 Q16 11 OUT R15 R5 -VAUX PA107DPU www.cirrus.com Copyright (c) Cirrus Logic, Inc. 2010 (All Rights Reserved) APR 2010 1 APEX - PA107DPUREVD PA107DP (R) Product Innovation From 1. CHARACTERISTICS AND SPECIFICATIONS ABSOLUTE MAXIMUM RATINGS Parameter SUPPLY VOLTAGE, +VS to -VS SUPPLY VOLTAGE, -VS SUPPLY VOLTAGE, -VAUX to +VAUX SUPPLY VOLTAGE, -VAUX OUTPUT CURRENT, Steady State, (Within SOA) OUTPUT CURRENT, peak, (Within SOA) POWER DISSIPATION, internal, DC INPUT VOLTAGE TEMPERATURE, pin solder, 10s TEMPERATURE, junction TEMPERATURE RANGE, storage OPERATING TEMPERATURE, case (Note 2) -40 -25 -VAUX + 2 Symbol Min 40 -20 20 -10 Max 200 -100 36 -18 1.5 5 62.5 +VAUX - 2 260 150 +85 +85 Units V V V V A A W V C C C C SPECIFICATIONS Parameter Test Conditions VS = 100V, -VS = -100V, VAUX = 15V, -VAUX = -15V INPUT OFFSET VOLTAGE OFFSET VOLTAGE vs. temperature BIAS CURRENT, initial INPUT RESISTANCE, DC INPUT CAPACITANCE INPUT VOLTAGE RANGE NOISE, RTI GAIN OPEN LOOP GAIN @ DC OPEN LOOP GAIN @ 1MHz POWER BANDWIDTH, 170Vp-p OUTPUT VOLTAGE SWING VOLTAGE SWING CURRENT, peak CURRENT, Steady State (within SOA) SLEW RATE, 25% to 75% SETTLING TIME to 0.1% 2500 3000 12 10M in parallel with 10 pf IO = 1.5A VS 10 5 1.5 187 VP-P V A A V/S S Full temperature range 2 140 40 dB dB MHz 1k source, 500 kHz BW, ACL 101 -VAUX + 2 13 (Note 3) 13 2 +VAUX - 2 5 10 300 10 mV V/C pA G pF V nV/Hz Min Typ Max Units 2 PA107DPU (R) Product Innovation From PA107DP Test Conditions Min 20 -100 10 -18 20 20 15 -15 30 30 19 19 Parameter POWER SUPPLY VOLTAGE, +VS VOLTAGE, -VS VOLTAGE, +VAUX VOLTAGE, -VAUX CURRENT, QUIESCENT, +VS CURRENT, QUIESCENT, -VS CURRENT, QUIESCENT, -VAUX CURRENT, QUIESCENT, +VAUX THERMAL RESISTANCE, AC, junction to case (Note 6) RESISTANCE, DC junction to case RESISTANCE, junction to air TEMPERATURE RANGE, case Typ Max 100 -20 18 -10 35 35 21 21 1.5 2 30 Units V V V V mA mA mA mA C/W C/W C/W C -25 85 NOTES: 1. All Min/Max characteristics and specifications are guaranteed over the Specified Operating Conditions. Typical performance characteristics and specifications are derived from measurements taken at typical supply voltages and TC = 25C. 2. Long term operation at the maximum junction temperature will result in reduced product life. Derate power dissipation to achieve high MTTF. 3. Doubles for every 10C of case temperature increase. 4. +VS and -VS denote the positive and negative supply voltages to the output stages. 5. +VAUX and -VAUX denote the positive and negative supply voltages to the input stages. 6. Rating applies if the output current alternates between both output transistors at a rate faster than 60Hz. EXTERNAL CONNECTIONS IN 1 C3 1uF +VAUX -VAUX GND OPEN OPEN OPEN +VS 2 3 C4 1uF C5 1uF C6 1uF 4 5 6 7 8 -VS 9 -VSP OUT +VSP 10 11 12 C1 + + C2 C1-2 = 10uF/A out (peak), electrolytic/tantalum, low frequency bypass. C3-4 = 1uF 25V X7R ceramic capacitor recomended. C5-6 = 1uF 200V X7R ceramic capacitor recomended. 12-pin SIP Package Style DP Formed leads available See Package Style EE PA107DPU 3 PA107DP (R) Product Innovation From 2. TYPICAL PERFORMANCE GRAPHS HIGH VOLTAGE SMALL SIGNAL RESPONSE 45 0 Amplitude Normalized Supply Current, IQ (X) 160 120 LOW VOLTAGE SMALL SIGNAL RESPONSE 45 0 160 120 1.02 1 0.98 0.96 0.94 0.92 0.9 0.88 0.86 0.84 HIGH VOLTAGE SUPPLY CURRENT Amplitude, (dB) Phase, () 80 40 Phase 0 Phase, () -45 -90 -45 -90 Amplitude 80 40 Phase 0 -135 -180 -135 -180 Amplitude, (dB) -40 10 100 1K 10K 100K 1M 10M 100M Frequency, (Hz) VS = 100V, VAUX = 15V -40 10 100 1K 10K 100K 1M 10M 100M Frequency, (Hz) VS = 20V, VAUX = 10V 0.82 40 60 80 100 120 140 160 180 200 Rail to Rail Supply Voltage, VSS (V) VAUX = 15V RESPONSE to 500KHz SQUARE WAVE 100 80 60 100 60 POSITIVE SLEW 100 60 NEGATIVE SLEW Amplitude, VO (V) Amplitude, (V) 20 0 -20 -40 -60 -80 Amplitude, (V) 40 20 -20 -60 20 -20 -60 -100 0 2 0.8 1.2 1.6 Time, T (s) A = -22, VS = 100V, VAUX = 15V 0.4 -100 0.0n 40n 60n 80n 100n Time, (ns) A = -22, VS = 100V, VAUX = 15V 20n -100 0.0n 40n 60n 80n 100n Time, (ns) A = -22, VS = 100V, VAUX = 15V 20n Normalized Quiescent Current, IQ(VS) (X) Internal Power Dissipation, PD (W) 90 80 70 60 50 40 30 20 10 0 0 POWER DERATING AC Power HIGH VOLTAGE CURRENT vs. TEMPERATURE 1.15 1.1 350 HIGH VOLTAGE CURRENT vs. FREQUENCY VS = 100V VAUX = 15V 10pF Load VO = 170VP-P Sinewave HV Supply Current, IVS (mA) -20 0 20 40 60 Case Temperature, TC (C) 80 300 250 200 150 100 50 1.05 1 DC Power 0.95 0.9 -40 25 50 75 100 125 150 Case Temperature, TC (C) 0 100 600 1100 1600 2100 2600 3100 Output Frequency, FOUT (KHz) 4 PA107DPU (R) Product Innovation From PA107DP PIN DESCRIPTIONS Pin # 1 2 3 4 5 6 7 8 9 10 11 12 +VS -VS -VSP OUT +VSP Pin name IN +VAUX -VAUX GND Description Summing Junction Input for Inverting Operational Amplifier +10V to +18V Supply for Input Circuits -10V to -18V Supply for Input Circuits Ground Open Pin Open Pin Open Pin +20V to +100V Supply for Gain and Gate Driver Circuits -20V to -100V Supply for Gain and Gate Driver Circuits -20V to -100V Supply for Output Source Follower High Power Output of Amplifier +20V to +100V Supply for Output Source Follower 3. GENERAL Please read Application Note 1 "General Operating Considerations" which covers stability, power supplies, heat sinking, mounting, current limit, SOA interpretation, and specification interpretation. Visit www.cirrus.com for design tools that help automate tasks such as calculations for stability, internal power dissipation, current limit, heat sink selection, complete Application Notes library, Technical Seminar Workbook and Evaluation Kits. CAUTION In order to achieve the highest speed with limited space short circuit protection and thermal protection were sacrificed. Do not short the output. Note that if current limiting at 1.5 A could be used, and the output was shorted, internal dissipation would be 150 W. This would still destroy the amplifier, albeit more slowly. 4. INTERNAL POWER DISSIPATION AND HEATSINK SELECTION With the unique combination of high voltage and speed of the PA107, traditional formulas for heatsink selection will falsely lower the apparent power handling capability of this amplifier. To more accurately predict operating temperatures use Power Design1 revision 10 or higher, or use the following procedure: Find internal dissipation (PD) resulting from driving the load. Use Power Design or refer to Apex Applications Note 1, General Operating Considerations, paragraph 7. Find total quiescent power (PDQ) by multiplying 0.035 A by VSS (total supply voltage), plus 0.021 times the total VAUX (+VAUX + |-VAUX|). Find output stage quiescent power (PDQOUT) by multiplying 0.001 by VSS. Calculate a heatsink rating which will maintain the case at 85C or lower. ROSA = TC - TA -0.1C/W PD + PDQ Where: TC = maximum case temperature allowed TA = maximum ambient temperature encountered ROSA = TJ - TA - (PD + PDQOUT) * ROJC -0.1C/W PD + PDQ Calculate a heatsink rating which will maintain output transistor junctions at 150C or lower. Where: TJ = maximum junction temperature allowed. ROJC = AC or DC thermal resistance from the specification table. Use the larger heatsink of these two calculations. Power Design is an Excel spreadsheet available free from www.cirrus.com PA107DPU 5 PA107DP 5. REACTIVE LOADS (R) Product Innovation From The PA107DP is stable at a gain of 20 or above when driving either inductive or capacitive loads. However an inductor is essentially a short circuit at DC, therefore there must be enough resistance in series to keep low frequency power within ratings. When driving a 1nF capacitive load with a 180 VP-P square wave, the current peak is 1 A. Driving the same capacitor with a 2.3 MHz sine wave, the power bandwidth frequency, results in 2.6 AP-P. The power dissipated in the amplifier while driving a purely capacitive load is given by the formula: P = 2VPKVS/XC P = 2IPKVS/ Where: VPK = Peak Voltage VS = Supply Voltage XC = Capacitive Reactance Notice that the power increases as VPK increases, such that the maximum internal dissipation occurs when VPK is maximum. The power dissipated in the amplifier while driving 1 nF at 2.3 MHz would be 82.76 W. This would not be a good thing to do! But driving 1 nF at 1 MHz at 180VP-P would result in 36.0 W, which could be within the AC power rating. This formula is optimistic; it is derived for an ideal class B amplifier output stage. 6. FEEDBACK CONSIDERATIONS The output voltage of an unloaded PA107DP can easily go as high as 95 V. All of this voltage can be applied across the feedback resistor, so the minimum value of a 1/2 W resistor in the feedback is 18050. Practically, 20K is the minimum value for a un-derated 1/2 W feedback resistor. In order to provide the maximum slew rate, power bandwidth, and useable gain bandwidth; the PA107DP is not designed to be unity gain stable. It is necessary to add external compensation for gains less than 20. Often lower performance op-amps may be stabilized with a capacitor in parallel with the feedback resistor. This is because there is effectively one additional pole affecting the response. In the case of the PA107DP, however there are multiple poles clustered near 30 MHz, therefore this approach does not work. A method of compensation that works is to choose a feedback capacitor such that the time constant of the feedback capacitor times the feedback resistor is greater than 33 n-seconds. Also install a capacitor from pin 1 to ground, the summing junction, greater than 20 times as large as the feedback capacitor. The feedback capacitor or summing junction capacitor without the other will degrade stability and often cause oscillation. With the compensation described the closed loop bandwidth will be the reciprocal of 2FB. Alternatively, at the expense of noise and offset, the amplifier can be stabilized by a resistor across the summing junction such that the parallel combination of the input resistor and summing junction resistor is less than a twentieth of the value of the feedback resistor. Note that this will increase noise and offset by to 20 times the RTI values, but with 10 mV max offset and 13 nV/(Hz)1/2 noise, performance will be acceptable for many applications. As seen by the very small values of capacitance used in compensation for low gain, stray feedback capacitance and/or summing junction capacitance can have a VERY large effect on performance. Therefore stray capacitance must be minimized in the layout. The summing junction lead must be as short as possible, and ground plane must be kept away from the summing junction lead. 7. SLEW RATE AND FULL POWER BANDWIDTH In the PA107DP the slew rate is measured from the 25% point to the 75% point of a 180VP-P square wave. Slew rate is measured with no load and with auxiliary supplies at a nominal 15 V and VS supplies at a maximum 100V. Power bandwidth is defined as the highest frequency at which an unloaded amplifier can have an undistorted sine wave at full power as its output. This frequency can be calculated as the slew rate divided by times the peak to peak amplitude; which would be 4.7 MHz for the PA107DP. Unfortunately running full output at this frequency causes internal dissipation of up to 107 W, well over the power limits for the PA107DP. Cutting the frequency to 2 MHz reduces internal dissipation to 34 W, acceptable with a good heatsink. 6 PA107DPU (R) Product Innovation From PA107DP SOA OUTPUT CURRENT FROM +VS or -VS (A) 5 t= 10 8. SAFE OPERATING AREA (SOA) The MOSFET output stage of this power operational amplifier has two distinct limitations: 1. The current handling capability of the MOSFET geometry and the wire bonds. 2. The junction temperature of the output MOSFETs. NOTE: The output stage is protected against transient flyback. However, for protection against sustained, high energy flyback, external fast-recovery diodes should be used. s 0m e st 1 ad ta ys te = TC te = TC 25 e st ad ta ys 9. SAFE OPERATING CURVES C 85 C The safe operating area curves define the maximum additional internal power dissipation the amplifier can tolerate when it produces the necessary output to drive an external load. This is not the same as the absolute maximum internal power dissipation listed elsewhere in the specification since the quiescent power dissipation is significant compared to the total. 0.1 1 10 100 200 SUPPLY TO OUTPUT DIFFERENTIAL VOLTAGE, VS - VO (V) 10. TYPICAL APPLICATION +VS +15V RF RIN IN GND +VSP +VS +V AUX OUT -VAUX Piezo Drive DAC PA107 -VSP -VS -VS -15V CONTACTING CIRRUS LOGIC SUPPORT For all Apex Precision Power product questions and inquiries, call toll free 800-546-2739 in North America. For inquiries via email, please contact apex.support@cirrus.com. International customers can also request support by contacting their local Cirrus Logic Sales Representative. To find the one nearest to you, go to www.cirrus.com IMPORTANT NOTICE Cirrus Logic, Inc. and its subsidiaries ("Cirrus") believe that the information contained in this document is accurate and reliable. However, the information is subject to change without notice and is provided "AS IS" without warranty of any kind (express or implied). Customers are advised to obtain the latest version of relevant information to verify, before placing orders, that information being relied on is current and complete. All products are sold subject to the terms and conditions of sale supplied at the time of order acknowledgment, including those pertaining to warranty, indemnification, and limitation of liability. No responsibility is assumed by Cirrus for the use of this information, including use of this information as the basis for manufacture or sale of any items, or for infringement of patents or other rights of third parties. This document is the property of Cirrus and by furnishing this information, Cirrus grants no license, express or implied under any patents, mask work rights, copyrights, trademarks, trade secrets or other intellectual property rights. Cirrus owns the copyrights associated with the information contained herein and gives consent for copies to be made of the information only for use within your organization with respect to Cirrus integrated circuits or other products of Cirrus. This consent does not extend to other copying such as copying for general distribution, advertising or promotional purposes, or for creating any work for resale. CERTAIN APPLICATIONS USING SEMICONDUCTOR PRODUCTS MAY INVOLVE POTENTIAL RISKS OF DEATH, PERSONAL INJURY, OR SEVERE PROPERTY OR ENVIRONMENTAL DAMAGE ("CRITICAL APPLICATIONS"). CIRRUS PRODUCTS ARE NOT DESIGNED, AUTHORIZED OR WARRANTED TO BE SUITABLE FOR USE IN PRODUCTS SURGICALLY IMPLANTED INTO THE BODY, AUTOMOTIVE SAFETY OR SECURITY DEVICES, LIFE SUPPORT PRODUCTS OR OTHER CRITICAL APPLICATIONS. INCLUSION OF CIRRUS PRODUCTS IN SUCH APPLICATIONS IS UNDERSTOOD TO BE FULLY AT THE CUSTOMER'S RISK AND CIRRUS DISCLAIMS AND MAKES NO WARRANTY, EXPRESS, STATUTORY OR IMPLIED, INCLUDING THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR PARTICULAR PURPOSE, WITH REGARD TO ANY CIRRUS PRODUCT THAT IS USED IN SUCH A MANNER. IF THE CUSTOMER OR CUSTOMER'S CUSTOMER USES OR PERMITS THE USE OF CIRRUS PRODUCTS IN CRITICAL APPLICATIONS, CUSTOMER AGREES, BY SUCH USE, TO FULLY INDEMNIFY CIRRUS, ITS OFFICERS, DIRECTORS, EMPLOYEES, DISTRIBUTORS AND OTHER AGENTS FROM ANY AND ALL LIABILITY, INCLUDING ATTORNEYS' FEES AND COSTS, THAT MAY RESULT FROM OR ARISE IN CONNECTION WITH THESE USES. Cirrus Logic, Cirrus, and the Cirrus Logic logo designs, Apex Precision Power, Apex and the Apex Precision Power logo designs are trademarks of Cirrus Logic, Inc. All other brand and product names in this document may be trademarks or service marks of their respective owners. PA107DPU 7 |
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